An approach for analyzing coupling rc interconnect delay based on "effective capacitance" is presented.

基于“有效电容”的概念提出了一种分析两相邻耦合r C互连延时的方法。

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Due to the large load capacitance and increasingly serious inter-wire coupling, deep submicron buses are facing many problems like power, delay and reliability.

大的负载电容和日益严重的线间耦合使得深亚微米总线面临着功耗、延迟和可靠性等问题。

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