An increase in chip area and circuit complexity leads to a reduction in the yield of chip production. In order to get a fair yield, the fault tolerant technique is introduced into the IC design.

随着芯片面积的增加及电路复杂性的增强，芯片的成品率逐渐下降，为了保证合理的成品率，人们将容错技术结合入了集成电路。

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An increase in chip area and circuit complexity leads to a reduction in the yield of chip production. In order to get a fair yield, the fault tolerant technique is introduced into the IC design.

随着芯片面积的增加及电路复杂性的增强，芯片的成品率逐渐下降，为了保证合理的成品率，人们将容错技术结合入了集成电路。

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