A sense amplifier circuit for reading the state of memory cells.
本发明提供一种用于读取存储器单元的状态的读出放大器电路。
Some Suggestions of improving the sense amplifier design are made.
本文还对读出放大器的设计提出了若干改进建议。
Low-Cost, Micropower, High-Side Current-Sense Amplifier Comparator Reference.
低成本，微功耗，高边电流检测放大器，比较器参考。
As shown in Fig. 1 and Fig. 1, an example of a sense amplifier is illustrated.
如在图1及图1中所示，图解说明一检测放大器的实例。
Especially when he to close your eyes, the other five will be a sense amplifier.
尤其是当他闭上眼睛的时候，其他五感就会放大几分。
The sense amplifier is improved from trigger sense amplifier which is usually for DRAM.
灵敏放大器从触发器性灵敏放大器改进而来，后者一般用于DRAM中。
A pulse to gate the output of a core memory sense amplifier into a trigger in a register.
将磁心存储器读出放大器的输出选通到寄存器的触发器中的一种脉冲。
Using simulation techniques, we have made some improvement for design of the sense amplifier.
借助于计算机的模拟计算，对于读出放大器的设计作了一些改进。
Sense Amplifier is nowadays widely used in the memory system design, IO design to improve speed.
灵敏放大器广泛地应用于存储器系统和IO设计中。
The crucial path includes address buffer, decoder, memory unit, sense amplifier and output buffer.
其中包括地址缓冲、译码器、存储单元、灵敏放大器和输出缓冲电路。
A sense amplifier control signal generating circuit of a semiconductor memory apparatus is provided.
从某种意义上说放大器控制信号产生的半导体存储器设备电路提供。
The semiconductor memory device includes a bit line sense amplifier connected to a pair of bit lines.
该半导体存储器件包含连接到一对位线的位线感测放大器。
A novel current mode sense amplifier with high read-speed for non-volatile memory application is developed.
对此，设计出一种具有较快读取速度的新型电流灵敏放大器。
The whole circuit includes memory array, decode, sense amplifier, data in - out circuit and pre - charge circuit.
电路包括存储阵列、译码电路、敏感放大器、数据输入输出电路，预充电电路等部分。
A sense amplifier includes a first sensing element and a second sensing element redundant to the first sensing element.
感测放大器包括第一感测元件和对于第一感测元件是冗余的第二感测元件。
A fast access time is achieved by using six-transistor CMOS memory cell, latched sense amplifier, and high-speed decoder circuit.
存储器采用六管CMOS存储单元、锁存器型敏感放大器和高速译码电路，以期达到最快的存取时间。
The state of the memory element can thereby be detected by a voltage comparator sense amplifier that is connected to the bit line.
因此可通过连接到位线的电压比较器读出放大器来检测存储器元件的状态。
In various embodiments of the invention, a memory device includes at least one sense amplifier with an asymmetrical configuration.
在本发明的各实施例中，一种存储装置包含呈不对称配置的至少一个检测放大器。
A sense amplifier control signal generating unit receives the timing control signal and generates a sense amplifier control signal.
从某种意义上说放大器控制信号产生单位接收时序控制信号，并生成检测放大器控制信号。
A fast access time is obtained by utilizing a bit line equalizing technique, a high speed hierarchical sense amplifier and a preset data output buffer.
采用位线平衡技术、高速两级敏感放大器及可预置电压的数据输出缓冲，以提高存储器的读写频率。
The study is focused on the EEPROM special periphery circuits, including the charge pump, high voltage switch, sense amplifier and other related circuits.
其中着重研究了EEPROM的特色电路，包括电荷泵，高压转换电路，灵敏放大器及其它相关电路。
The sense amplifier circuit is commonly symmetrical which needs a matched layout design, so the system design and layout design is also discussed at the end.
通常情况下，灵敏放大器均设计为对称结构，对版图有着很高的对称要求，最后也对系统和版图设计做了简要讨论。
This thesis first analyzes basic design of sense amplifier in deep sub-micron system, compares and discusses the mismatch problem, and then the new design is presented.
本文首先分析传统设计的问题，然后针对深亚微米系统，对失配产生的问题进行比较分析，在此基础上提出改进方法和新型结构。
Timing adjusting circuits have a ferroelectric capacitor for timing adjustment in transmitting the activation signals output from the column decoder to the sense amplifier circuits.
定时调整电路具有铁电电 容器，用于在把从列解码器输出的激活信号发送到检测放大器电路时进 行定时调整。
This paper describes computer-aided design of a sense amplifier circuit in a magnetic core memory. The sense amplifier circuit has been modified by analyzing its threshold characteristic.
本文概要地介绍了计算机辅助一种磁芯读放电路的改进设计，解析了读放电路的门槛特性，阐明了利用电路分析系统DFX-1对该电路的分析与设计。
High speed is achieved by using current mode techniques, which include designing optimum register cell, new high speed current sense amplifier and sense amplifier control signal generator.
在电流工作方式下，通过设计优化的存储单元、新型高速电流灵敏放大器以及一种灵敏放大器控制信号产生电路，提高了寄存器堆的读取速度。
The sense amplifier further comprises a switch circuit configured to switch between the first and second sensing elements when an offset of the sense amplifier is greater than a prescribed amount.
感测放大器还包括被配置为在感测放大器的偏移大于规定量时在第一和第二感测元件之间切换的开关电路。
The circuit is divided into full bridge module, charge sense amplifier module, correlated double sampling and holding module, closed-loop feedback module, low-pass filter and time controlling module.
检测电路分为全桥平衡模块、电荷放大器模块、信号放大模块、相关双采样模块、采样保持模块、闭环反馈模块、低通滤波模块和数字时序控制模块。
In such cases, the unused amplifier should be connected as a unity-gain follower (force and sense pins tied together) and the input should be connected to ground.
同样的原因，不用的放大器应当成单位增益跟随器(驱动端和感测端接到一起)，且其输入端应接地。
In such cases, the unused amplifier should be connected as a unity-gain follower (force and sense pins tied together) and the input should be connected to ground.
同样的原因，不用的放大器应当成单位增益跟随器(驱动端和感测端接到一起)，且其输入端应接地。
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