The circuits used are Chua 'circuit and phase lock loop.
所用的电路为蔡氏电路和锁相环电路。
How to raise the phase lock speed of embedded DPLL is researched.
对如何提高嵌入式全数字锁相环的锁定速度进行了研究。
Digital phase lock loop is a key part of the digital demodulator.
数字锁相环是数字解调器的关键部件。
The Digital Phase Lock Loop(DPLL)is the core of the coherent demodulation.
数字锁相环路（DPLL）是数字相干解调技术的核心。
In the new scheme proposed, the phase lock loop is avoided and the digital logical circuit is used.
该方案利用信号自身的特性，采用数字逻辑设计，有效避免了性能不高的锁相环的使用。
The conduction of special cable and special phase lock loop technology makes high signal more accurate;
特种的传导电缆和特殊的锁相环技术使高度信号更精准；
Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.
基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。
The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.
环路为反馈结构，包括插值器、时钟误差检测和环路滤波器三个部分。
We have mainly researched two FM signal demodulation techniques called Frequency Spectrum Separation and Phase Lock Loop in the first part.
一次解调中研究了频谱分离法和锁相法两种实现鉴频的技术。
Phase lock loop and benchmark resistance compensating technologies were used to improve the detection precision, the error was less than 10%.
通过锁相放大技术及基准电阻补偿方法提高了测量的精度，误差在10%以内。
The general research on the theory and technology of sampling phase lock in the paper will make a basement for the development of new product.
本论文对取样锁相理论及技术的全面研究，为新产品开发做了一定的预研工作。
Digital phase lock loops are widely adapted in nowadays communication systems. However, it is difficult to design the loop parameter precisely.
数字锁相环在实际通信系统中应用广泛，但其精确的环路参数设计比较困难。
The orthogonal analog phase lock loop is used to get the timing information of the impulse radio system and the multi-path component separation.
使用正交模拟锁相环路对无载波的脉冲无线电系统实现多径捕获和同步提取。
The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。
By using a double phase lock in amplifier to measure the AC strain, the measurement error can be decreased to 0.4% of the total measurement range.
如果使用双相位锁相放大器测量交变的被测量，误差将减小到全量程的0.4%以内。
This paper mainly discusses the design and the application of the IGBT phase lock control circuit controlled by the induction heating power supply.
本文主要介绍IGBT锁相控制电路在感应加热电源控制系统中的设计和应用。
Phase lock oscillator, address coding and intermission mode are taken to stabilize the system and to promise the targets working period longer than 10 day.
系统中采用了锁相技术和地址编码，并采用间隙工作方式，使得本系统工作性能稳定，目标源一次充电可连续工作10天以上。
This paper discusses the influence of mixer on the phase lock-loop (PLL) circuit of a local oscillator. In mixer, local signal is produced by the PLL circuit.
本文讨论了采用锁相环路作为本振信号的混频器对本振锁相环路的影响。
In frequency synthesis by phase lock, the loop gain will vary by the same amount due to this effect, which generally im - pedes optimization of loop performance.
在锁相频率合成器中，由于压控灵敏度的变化，环路增益也将产生同样大小的变化，这就妨碍了环路特性的最佳化。
The phase-locked loop frequency synthesizer is a kind of phase lock installment and it is a kind of separate gap frequency code generator with high stability frequency.
锁相环频率合成器是一种相位锁定装置，是一种频率稳定度较高的离散间隔型频率信号发生器。
The primary factor affecting fast phase lock is analyzed by using MATLAB. Then a fast all digital phase locked loop with a high precision automatic modulus control is proposed.
应用MATLAB分析了影响锁相环快速锁定的主要因素，提出了一种具有高精度自动变模控制的快速全数字锁相环。
The phase lock loop is a feedback control system that makes two telecommunication signals' phase synchronization, suitable to the synchronous trigger circuit of the convertor device.
锁相环路是完成两个电信号相位同步的反馈控制系统，适宜于变流装置的同步触发电路之中。
A systematical analysis of dynamic characteristic of the pulse-synchronous camera control ystem is described, as to make the results help the researches in phase lock speed-stabilizing ystem.
本文对脉冲同步摄影机控制系统的动态特性进行了系统的分析，以便使所得结果对锁相稳速系统等方面的研究有所帮助。
Therefore, the frequency synthesizer works in millimeter wave band is mostly designed and realized by the way of indirect phase lock frequency synthesis, based on specific integrated circuit.
广泛采用的直接数字式频率合成方法，却面临输出频率上限难以提高和输出杂散的难以抑制两个难题。
This paper gives a detailed analysis of the principle of the phase lock circuit, one of the most important parts of the QF1052B Standard Signal Generator and provides some methods of checking it.
本文详细分析了QF1052B型标准信号发生器锁相环部分的基本组成及其工作原理，并提出了对此部分电路的检测方法。
The principle of phase lock loop and its application in the motor power-measuring system are introduced, furthermore the design and analysis of the circuit for constant speed control are provided.
介绍了摊铺机行驶控制系统的基本要求，以单边行驶回路为例探讨了其工作原理； 根据摊铺机对行驶速度的要求，分析了恒速控制技术，探讨了行驶系统控制方式。
Due to the frequency pulling of FLL, the passband of the filter in PLL can be made very narrow to suppress the noise, and the PLL can lock carrier's phase with high accuracy.
由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟踪载波相位的要求。
The task of a phase-lock receiver is to reproduce the original signal while removing as much of the noise as possible.
锁相接收机的作用是重建原信号而尽可能地去除噪声。
It is noted that the minimum mean square error (MMSE) detector often loses phase to lock a desired signal when the desired signal dips into a deep fade.
在实际通信系统中当信号处于深衰落时，最小均方误差(MMSE)检测器经常失去对信号的相位跟踪。
The synchronization and separation of the data and clock from floppy disk driver are one of phase-lock techniques' use in computer field.
对软磁盘的数据和时钟的同步和分离，只是锁相技术在计算机领域的应用之一。
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